This UART module was created for self-educating purposes and is WIP.
Finished:
- uart transmitter and receiver with 5-9 data bits, optional parity (odd/even) and 1-2 stop bits
- Makefile for ghdl + gtkwave flow
TODO:
- extensive testbench for verification
- example application project (Digilent Nexys A7)
- flow control (rts/cts)
- Add Wrapper with WBL/APB Slave and TX/RX FIFOs