Architecting post-Von Neumann AI infrastructure.

📖 Read The Tensorplane Manifesto

As generative AI models scale into the trillions of parameters and agentic workflows demand real-time state manipulation, traditional OS kernels have become the primary bottleneck. We build 0-kernel, 0-copy, NVMe-oF data planes and bare-metal virtualization frameworks that fuse compute, memory, and I/O into a single, deterministic fabric.

By treating the host CPU as a pure computational engine and offloading side-effects to hardware-accelerated structures, we eliminate context-switching jitter and feed AI accelerators at line rate.

• tensorplane: (In Development) The Agentic Control Plane. A Recursive Self-Improving AI Foundry driven by a Multi-Agent System (MAS) operating over the Model Context Protocol (MCP). It autonomously monitors telemetry, dynamically provisions cloud infrastructure, and orchestrates the underlying data planes.
• dataplane-emu: A hardware-accurate C++ emulation framework for direct-to-silicon data planes. Enables transparent POSIX interception (LD_PRELOAD) to route legacy workloads directly into user-space queues without application rewrites.
• monadic-hypervisor: (In Development) A mathematically verifiable, bare-metal virtualization architecture. It treats the host CPU as a pure computational engine by shifting all network and storage "side-effects" to out-of-band DPUs (e.g., NVIDIA BlueField-3). It leverages Scalable I/O Virtualization (SIOV) and PASID tracking to multiplex PCIe devices across hyperscale multi-tenant boundaries without host-CPU emulation overhead.
• ⚡🧠 m-store: The Unified Memory & State Orchestration Fabric. A zero-kernel, RDMA-first data plane designed to eliminate the AI "memory wall." m-store natively integrates with inference frameworks like vLLM (PagedAttention) and SGLang (RadixAttention) to provide a disaggregated Key-Value (KV) cache substrate. By leveraging SPDK and CXL 3.1 Global Integrated Memory, it completely bypasses the Linux kernel to swap massive context windows directly into GPU VRAM at bare-metal speeds.
• m-ipc: A bare-metal, hardware-assisted messaging framework. Built for RISC-V many-core scaled-up clusters to eliminate the "synchronization tax" using cache-pollution mitigation and zero-copy semantics.

We actively research and engineer at the intersection of:

• Bare-Metal Virtualization: Scalable I/O Virtualization (SIOV) and DPU/SmartNIC offloading.
• Hardware-Software Co-Design: ARM64 (Graviton) weak memory ordering optimizations and RISC-V custom extensions.
• Zero-Trust Agentic Gateways: Deterministic, hardware-isolated Model Context Protocol (MCP) routing.