Debug Module ongoing integration into Mocha

[alexandrecapltd]

This PR captures ongoing work to integrate the riscv-dbg module into mocha, following up on #303.

Currently,

• The pulp riscv-dbg module has been vendored
• The vendored lowrisc_ip now include the jtagdpi and tcp_server ips
• A jtagdpi instance has been added to hw/top_chip/dv/verilator/top_chip_verilator.sv and connected the top_chip_system module jtag pins.
• hw/top_chip/rtl/top_chip_system.sv now has a debug module instance connected through converter modules (dmi_jtag for the debug module interface, axi_adapter for the master interface and axi_to_mem for the slave interface). The jtag pins are exported. The debug_req_irq is connected to the CVA6 core, and the reset coming out of the debug module is in use (ndmreset_n = (~ndmreset) & rst_ni).
• In hw/top_chip/rtl/top_pkg.sv, the SoC configuration accounts for the added debug module.

This now builds for me, so I open this PR for others to be able to take a look.
I lifted the earlgrey openocd configuration from the opentitan repository. When simulating and trying to attach, the generated traces show traffic on the jtag interface, as well as a debug irq eventually being triggered. The CVA6 core which was emitting traffic on its noc_req signals goes silent, and openocd reports that the core failed to halt.

Things to investigate:

• Should some uses of ndmreset be using rst_ni?
• Is the specific version of the riscv-dbg module picked for vendoring the desired one?
• Is the set of patches (lifted from the opentitan repository ) currently applied the desired set?