FROMLIST: phy: qualcomm: qmp-combo: update DP PHY PLL programming on …#1012
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quicmahap wants to merge 1 commit intoqualcomm-linux:tech/mm/drmfrom
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FROMLIST: phy: qualcomm: qmp-combo: update DP PHY PLL programming on …#1012quicmahap wants to merge 1 commit intoqualcomm-linux:tech/mm/drmfrom
quicmahap wants to merge 1 commit intoqualcomm-linux:tech/mm/drmfrom
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…Glymur The existing DP PHY PLL and AUX configuration for the Glymur platform does not fully follow the Hardware Programming Guide requirements for DP over Type-C, which results in DP link bring-up failures. Update the DP PHY programming sequence and PLL-related register settings to align with the latest HPG recommendations. With this change, DP link training completes successfully on Glymur-based platforms. Fixes: d10736d ("phy: qualcomm: qmp-combo: Add DP offsets and settings for Glymur platforms") Signed-off-by: Ritesh Kumar <ritesh.kumar@oss.qualcomm.com> Signed-off-by: Mahadevan P <mahadevan.p@oss.qualcomm.com> Link: https://lore.kernel.org/all/a967d7ec-66f7-4eaa-91e3-0a96e5a8ec7f@oss.qualcomm.com/
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…Glymur
The existing DP PHY PLL and AUX configuration for the Glymur platform does not fully follow the Hardware Programming Guide requirements for DP over Type-C, which results in DP link bring-up failures.
Update the DP PHY programming sequence and PLL-related register settings to align with the latest HPG recommendations. With this change, DP link training completes successfully on Glymur-based platforms.
Fixes: d10736d ("phy: qualcomm: qmp-combo: Add DP offsets and settings for Glymur platforms")
Link: https://lore.kernel.org/all/a967d7ec-66f7-4eaa-91e3-0a96e5a8ec7f@oss.qualcomm.com/